Would it make sense to mate a Duet rcvr w external I2S DAC?

[Krishnafred]

hi,
I'm about to connect i2s from sbr to tda1541 in a cd player. Does anyone know what to do with pin 4 of the tda, it is somewhat different than the tda a version that works from pin 1,2 and 3 solely. Thanks.

[Pete Fowler]

hi,
I'm about to connect i2s from sbr to tda1541 in a cd player. Does anyone know what to do with pin 4 of the tda, it is somewhat different than the tda a version that works from pin 1,2 and 3 solely. Thanks.

At the risk of sounding ungracious to new posters - if you don't know what all the pins do, what are you doing mucking around with the chip? Read the spec sheet(s) and figure it out.

Then let us know what you find out... ;-)

Pete

[Krishnafred]

Hi Pete,

That answer doesn't help me lot. It's seems a waste of time struggling through useless forum messages that aren't to the point. Of course I already looked at the datasheet but it isn't totally clear to me for this chip so please feel honored someone of you knows better and is humble enough to explain it to the ignorant being myself the new one.

Thank you and regards.

[hybride]

Ok, first you have to open the magic box. Remove the 'sticker' on the bottom. Then you see the 4 little bolts. Then, the way to go for optimum I2S:

Connect (R17=MCK), R18=BCK, R19=DATA, R20=LRCK, to any DAC with I2S input

If you want to feed separate voltages: remove the Wifi board. On the main print you will see 2 regulators, both with a coil on the output. Remove the coils and inject 3.3 and 1.2 Volts if you like. The SBR will work on I2S and wired ethernet with only these 2 voltages!

Remove the 11.289 crystal and R104. Inject the new clock to pin 42 of the Xilinx or on the side of R104 which is connected to pin 42. Unsolder/disconnect pin 14 (vcc) from the 74HC04. With that you disable the 12mhz crystal and SPDIF. Pin 14 is the upper right pin when you have the SBR in normal position (led in front).

Tried to lower the voltage of the clock to 1.6V. It's really nice!

[jkeny]

Brilliant, Hans, just what I needed. I'll be getting to it in the next week or so but first I have to find out why there's a channel imbalance in my hastily modded Tripath TA2020 amp. Then I need to tidy up my Musiland DAC with shorter I2S cable & clock injection to ES9022 DAC. Then I want to tap I2S from the HiFace to a ES9022 & then the SBR mods.

Lots to do but in the end will have 3 units running I2S to ESS9022 DAC which will be a nice comparison platform

Edit: I also have a Tent clock but will have to check what speed it is - I'll be running off 3.3V batteries (if the correct speed) but will be interested in experimenting with lower voltages - as I said, I'm surprised it works below it's stated min V of 3.3V, though?

I got it now - it's the rubber base on the bottom that hides the bolts, not the sticker. I just lifted each corner to get at the four of them.

krishnafred, is the 4th pin for a MCLK clock signal? I haven't looked at the datasheet but older DACs need the I2S clock line whereas newer DACs only need the other 3 I2S lines & as local clock supply, I think.

[Pete Fowler]

Hi Pete,

That answer doesn't help me lot. It's seems a waste of time struggling through useless forum messages that aren't to the point. Of course I already looked at the datasheet but it isn't totally clear to me for this chip so please feel honored someone of you knows better and is humble enough to explain it to the ignorant being myself the new one.

Thank you and regards.

No, I don't suppose it helped much...so, looking at page 4 of the spec sheet I see:

Pin4 is used for feeding the right channel bitstream to the 1541 under certain conditions. It's unused otherwise. Do you know which way you want to use it?

More helpful?

[Pete Fowler]

I'll be running off 3.3V batteries (if the correct speed) but will be interested in experimenting with lower voltages - as I said, I'm surprised it works below it's stated min V of 3.3V, though?

In order to oscillate the Tent XO has an internal amplifier of some kind. That amp has a drop-out voltage and as long as you stay above it the XO should work. However, given the tolerance of amplifiers your XO could stop working at a higher or lower voltage than Hans'.

I'm guessing the improvement comes from not overdriving the input of the Xilinx chip with the clock signal.

krishnafred, is the 4th pin for a MCLK clock signal? I haven't looked at the datasheet but older DACs need the I2S clock line whereas newer DACs only need the other 3 I2S lines & as local clock supply, I think.

Good guess, but it's the reverse - the newer DACs take a master clock along with the I2S to reduce jitter. Older DACs like the TDA1543 only need the three I2S lines.

Cheers,

Pete

[Krishnafred]

Thank you very much,

The confusion was about this paragraph about input data selection:

With input OB/TWC connected to ground, data input (offset binary format) must be in time multiplexed mode. It is
accompanied with a word select (WS) and a bit clock input (BCK) signal. A separate system clock input (SCK) is provided
for accurate, jitter-free timing of the analogue outputs AOL and AOR.
With OB/TWC connected to VDD the mode is the same but data format must be in two’s complement.
When input OB/TWC is connected to (VDD1) the two channels of data (L/R) are input simultaneously via (DATA L) and
(DATA R),

Which one best to use with the squeezebox? I only had one data cable connected from the squeezebox and didn't have the r-data input thinking the tda would clock on that one data without a seperate clock which I prefer for now.

Regards

[Pete Fowler]

Thank you very much,

The confusion was about this paragraph about input data selection:

With input OB/TWC connected to ground, data input (offset binary format) must be in time multiplexed mode. It is
accompanied with a word select (WS) and a bit clock input (BCK) signal. A separate system clock input (SCK) is provided
for accurate, jitter-free timing of the analogue outputs AOL and AOR.
With OB/TWC connected to VDD the mode is the same but data format must be in two’s complement.
When input OB/TWC is connected to (VDD1) the two channels of data (L/R) are input simultaneously via (DATA L) and
(DATA R),

Which one best to use with the squeezebox? I only had one data cable connected from the squeezebox and didn't have the r-data input thinking the tda would clock on that one data without a seperate clock which I prefer for now.

Regards

I can help you to figure out the answer, but I won't give you the answer. A hint is you need to understand which of the three options for OB/TWC sets the 1541 chip to receive normal 3-wire I2S, which is what the Duet receiver sends out. Google on the I2S protocol and the answer should become clear.

(I'm really not a jerk, I just believe in helping people to learn vs. just handing out answers. It's not as convenient as a simple answer but you learn more in the process and eventually you won't have to put up with jerks like me...)

[Pete Fowler]

Tried to lower the voltage of the clock to 1.6V. It's really nice!

Hans,

Was there some voltage where the SQ improved significantly (like 2.1V) and after that it was gradual? Or was the effect more linear - as you descreased the XO voltage the sound improved steadily?

I'm trying to understand if there's a threshold on the XO voltage that gets us 90-95% there. A little voltage headroom is a good thing even with batteries. ;-)

Pete