Would it make sense to mate a Duet rcvr w external I2S DAC?

[Pete Fowler]

I'm a relative noob when it comes to digital so please bear with me - I'm trying to get my head around the I2S output of the Duet rcvr with hopes of tapping the bus directly to an I2S native external DAC (ie, NOS TDA1543 design). So here goes...

If I understand correctly, the Xilinx chip is responsible for converting incoming digital files (FLAC, etc) or streaming FM, etc, into I2S format for the Wolfson DAC. To do this it needs two crystal oscillators - 11.xxMHz for CD data and 12.xxMHz for FM, etc. The master clock also toggles between 44.1kHz and 48kHz depending on the music source, yes?

The Wolfson DAC takes I2S input but it also needs the master clock, so if I were to use an outboard DAC of similar design I'd need to tap a master clock line from the Xilinx along with the I2S lines, yes? Otherwise I'm stuck with CD-only or FM-only capability based on whatever master clock is on the external DAC circuit. This also eliminates reclocking the Duet using an external clock (I lose dual format capability).

Older DAC chips like the TDA1543 don't require a master clock feed. Would this allow me to simply feed the I2S coming out of the Xilinx to an external TDA1543-based DAC and use it for either CD or FM playback?

(Basically I'm trying to avoid S/PDIF out while keeping streaming FM compatibility).

Finally, would it improve the quality of the Xilinx output to replace both crystals with suitable low jitter clocks? I suspect the PS for the Xilinx will have to be cleaned up too. This should benefit the Wolfson and might sound good enough that I could avoid an external DAC. My guess is there's no way to predict - have to build it and see...

(I might try this first - maybe I won't need an external DAC if the clock/PS cleanup would improve things)

Sorry for rambling - just trying to figure it all out and decide whether it makes sense to tap the I2S bus to get less jitter/reflections than using an S/PDIF to I2S converter in an outboard DAC.

Cheers,

Pete

[RioTubes]

you discussed several potential mods; some of which can be done together (psu upgrade and better clock) while some are alternatives (slaving the transport to your dac versus upgrading the clock in the SB). You could start with the simpler mods of replacing the power supply and installing a better 11.2896 mHz clock. I like the price/performance of the Tent clocks. Yet its best to power the clock with its own regulated power supply. You could then assess your level of satisfaction with these improvements.

The more time consuming alternative is tapping the i2s signals and sending these out and into your dac box, and possibly slaving the receiver to your dac by locating the mclk in the dac. I'm not sure about your tda1543...I do this with the TDA1541a. Here's how I did it (see link). If you were to pursue this type of syncrhonous reclocking circuit then an implementation around the receiver would be simpler because it is already i2s whereas the SB2 and SB3 were left justified format that needed to be converted to i2s (one function of the synchronous reclocking board shown in the link). This is a tedious project if done point-to-point so you might start with your other ideas and see if you are satisfied with the results. One consequence of this circuit is that it defeats the radio unless you add add'l circuitry.

http://audiogestalt.wordpress.com/

[Pete Fowler]

you discussed several potential mods; some of which can be done together (psu upgrade and better clock) while some are alternatives (slaving the transport to your dac versus upgrading the clock in the SB).

Yes and no - I have no plans to slave the SB to an external clock since I would lose streaming FM. I enjoy the FM feeds as much as my CD's. Slaving is not an alternative for me in this case (but I can understand why one might want to do it).

You could start with the simpler mods of replacing the power supply and installing a better 11.2896 mHz clock. I like the price/performance of the Tent clocks. Yet its best to power the clock with its own regulated power supply. You could then assess your level of satisfaction with these improvements.

I agree with you on this, although I'm also thinking to install a 12.xxx Tent clock for the FM (IIRC, the Tent shunt PS boards have enough power to handle two Tent clocks). I am hoping the FM would improve in the same way that the CD playback 'should' with a better clock. The question is - will the I2S output of the Xilinx chip improve significantly with better clock(s) and a cleaner 3.3V power supply?

(Am I kidding myself here? Is the Xilinx a weak link? Does the cost vs. benefit make sense?) Silk purses and pig's ears... ;-)

I forgot to mention I've already replaced the Duet's wall-wart SMPS with a linear 9V regulated supply which helped a lot. The next step would be to clean up the supply for the Xilinx somehow. I think. Maybe. Oof!

The more time consuming alternative is tapping the i2s signals and sending these out and into your dac box, and possibly slaving the receiver to your dac by locating the mclk in the dac. I'm not sure about your tda1543...I do this with the TDA1541a. Here's how I did it (see link). If you were to pursue this type of syncrhonous reclocking circuit then an implementation around the receiver would be simpler because it is already i2s whereas the SB2 and SB3 were left justified format that needed to be converted to i2s (one function of the synchronous reclocking board shown in the link). This is a tedious project if done point-to-point so you might start with your other ideas and see if you are satisfied with the results. One consequence of this circuit is that it defeats the radio unless you add add'l circuitry.

http://audiogestalt.wordpress.com/

Thanks - I've visited your site before. Very good info!

Reading between the lines of your reply, it seems the Duet master clock does toggle when playing FM vs CD sources - correct?

I'm not up for reclocking the Duet rcvr - I really want to keep the FM capability of the unit (too many good stations out there). If the TDA1543 can run on whatever comes over the 3 line I2S bus then I could feed something like a DDDAC1543 or other NOS TDA1543-based DAC from it. At first glance it seems do-able. But I'm guessing...

Thanks for the info!

Pete

[fibcouple]

Older DAC chips like the TDA1543 don't require a master clock feed. Would this allow me to simply feed the I2S coming out of the Xilinx to an external TDA1543-based DAC and use it for either CD or FM playback?

(Basically I'm trying to avoid S/PDIF out while keeping streaming FM compatibility).

Pete

If you can get the i2s signals from the duet, then tda1543 or tda1541a will accept these signals directly. These dacs dont need a masterclock input but reclocking these signals with a low jitter clock (Tent or superclock4 which I use for my nos tda1541a s1) will definitely improve the sq. Very important here will be however the quality of the psu as clocks really shine when fed with clean regulated supply, and they also inject noise in the circuit (afaik) if fed by psu feeding dac, other digital chips etc.

If you want to tap i2s, you will need to make sure the impedance is matched. I am not an expert on this but asking question from Steve Nugent on another forum, I believe you need a 75 or 110 ohm cable. Grounds for the three i2s lines have to be separate, even though if they are tied to same ground at the source and the destination. I understand you need to put resistors in series (22 ohms onwards, less than impedance of the cable) very close to i2s generating chip so the sum of the output impedance of the chip & the resistor value equals the cable impedance. In lot of circuits available on the web, there are resistors placed just before the dac chips as 'damping' resistor' but the gentleman mentioned above seems to disagree with that, and I personally dont know the answer. I am still learning but I hope this info adds to your knowledge bank.

I'm not sure about your tda1543...I do this with the TDA1541a. Here's how I did it (see link). If you were to pursue this type of syncrhonous reclocking circuit then an implementation around the receiver would be simpler because it is already i2s whereas the SB2 and SB3 were left justified format that needed to be converted to i2s...................

Hi Riotubes

I have also visited your excellent site before. Thanks for taking time to put all this info together & thanks to John Swenson for sharing the knowledge as well.

Could you please tell how the reclcoking circuit will differ if Pete were to have native i2s coming out of the duet? I am also interested in making that board but do not have the knowledge to design anything myself. Thanks.

Regards

Fib

[Pete Fowler]

I am still learning but I hope this info adds to your knowledge bank.

Regards

Fib

Fib,

Yes! Thank you - this is exactly the discussion I was hoping for. Good info! :-)

Pete

[RioTubes]

Pete - I have read observations by others that replacing the 11.2896 mHz oscillator is productive. Wise to add a clean regulated supply...if one chose a Tent XO, then the Tent shunt reg would be the natural choice. I don't use the radio so can't add anything there.

i2s signal degrades very rapidly over just a half dozen centimeters or so. If you don't plan to reclock/resynch in your dac it really would be a big step down from the current spdif interface. There are posts on this board and also on diyparadise on improving the current spdif interface.

If you do decide to tap the i2s signals in the receiver, you do so *on the dac side* of each resistor that is soldered in each of 3 traces that runs between the xilinx and dac chip pins. This is what I think Fib is referring to. The resistors should be there already (at least in my SB2) so you don't have to add them. In your dac box, damping resistors (~22 ohm) can be installed just before the pins on the dac that accept the signals.

Note that the TDA1543 uses i2s, whereas TDA1543a uses the right justified Japanese format. The duet receiver generates i2s signals so one needs to ensure this is compatable with the Dac's format.

Fib - I'd like to help with a redesign of the synchronous reclocking board, but clock design is above my pay grade. The reclocking board will be simpler because there will be no need to convert the signal format for your tda1541a dac. You might try posting on diyaudio and linking to the layout of my board and requesting a pin reassignment. Most changes will focus on the 74 chip. Good luck!

[Pete Fowler]

Pete - I have read observations by others that replacing the 11.2896 mHz oscillator is productive. Wise to add a clean regulated supply...if one chose a Tent XO, then the Tent shunt reg would be the natural choice. I don't use the radio so can't add anything there.

i2s signal degrades very rapidly over just a half dozen centimeters or so. If you don't plan to reclock/resynch in your dac it really would be a big step down from the current spdif interface. There are posts on this board and also on diyparadise on improving the current spdif interface.

If you do decide to tap the i2s signals in the receiver, you do so *on the dac side* of each resistor that is soldered in each of 3 traces that runs between the xilinx and dac chip pins. This is what I think Fib is referring to. The resistors should be there already (at least in my SB2) so you don't have to add them. In your dac box, damping resistors (~22 ohm) can be installed just before the pins on the dac that accept the signals.

Note that the TDA1543 uses i2s, whereas TDA1543a uses the right justified Japanese format. The duet receiver generates i2s signals so one needs to ensure this is compatable with the Dac's format.

Rio,

Many thanks for your post(s)!

I will get cracking on a Tent XO and shunt reg for the CD ckt. Last night I was listening to FM and it actually sounds more open and transparent than my CD's at the moment - I'll leave the FM ckt alone for now and focus on the CD side. (Could this be due to a clean FM oscillator? I really don't think I'm imagining it)

I may need to rethink using I2S - are you saying that 'any' tap of the I2S bus will be worse than SPDIF, or that it will only be worse if I run more than a few cm to the outboard DAC? I was thinking of using miniature coax for each line with about a 6" run between the Duet and the DAC - too far?

Just wanted to be sure I understood your meaning...I got this idea from reading a 2006 post from John Swenson in the Audiophile forum:

http://forums.slimdevices.com/showthread.php?t=24800

Any thoughts on how to clean up the power to the Xilinx chip? That's where a lot of the action happens. I don't think the Tent 3.3V shunt reg has the current capacity to swap for the 3.3V switching supply on the Duet board. Any cost vs. benefit ideas on this?

All very enlightening (and keeps me from screwing up).

Pete

[ar-t]

If you are a "digital noob", then why are you attempting it? It can obviously be done, but it may require more skill(s) than you have perfected to really work well.

OK, sure you can put a better clock in, ahead of the Xilinx. And put a "better" supply on it. Why do you think that will assure a clean clock coming out of it?

Then you have to worry about how and where to return all the grounds. If you use cables, what type, what will their impedance be, and how will you drive them? And how not to create tons of EMI and/or horrible glitches on the signals.

It might be easier to stick with SPDIF and clean up the clock at the DAC end. After all, that is where the really clean clock need to be anyway.

Pat

[Pete Fowler]

If you are a "digital noob", then why are you attempting it? It can obviously be done, but it may require more skill(s) than you have perfected to really work well.

OK, sure you can put a better clock in, ahead of the Xilinx. And put a "better" supply on it. Why do you think that will assure a clean clock coming out of it?

Then you have to worry about how and where to return all the grounds. If you use cables, what type, what will their impedance be, and how will you drive them? And how not to create tons of EMI and/or horrible glitches on the signals.

It might be easier to stick with SPDIF and clean up the clock at the DAC end. After all, that is where the really clean clock need to be anyway.

Pat

All good assertions, Pat. I can't argue with any of them. But let me answer your question as to why I'm attempting it...

Sadly, being a relative noob, the only way I know to cure my ignorance is to start doing and learning, asking questions of those who do know better, and see where I end up. If a technically optimized result was my only goal then you are correct - I should hang it up. But I'm in this as much for the learning and experimenting as I am for the final result (this being the DIY forum and all). I also used to work in an R&D lab (I wrote firmware, didn't design the hardware), so I'm passing familiar with the pitfalls of trying to retrofit 'fixes' into existing systems. Esp small, highly optimized ones. With this in mind...

OK, sure you can put a better clock in, ahead of the Xilinx. And put a "better" supply on it. Why do you think that will assure a clean clock coming out of it?

If you reread my post you'll see I don't think it will assure a clean clock - I'm asking if it will (or not), and hoping for a cogent and helpful answer either way. The same for my other ideas - asking with an open mind, not assuming and hoping for confirmation. Does X work this way? Will Y respond well to a cleaner power supply? All reasonable and valid questions if one is trying to learn and understand, yes? Finally, I ask several times if the cost vs. benefit makes sense as I'm not aware of the gotchas from a system design perspective. Being a noob and all.

So...

Pete

[ar-t]

I will be more than happy to pass on my knowledge, as my time allows. You came here to share and learn. I can help with the latter.

OK......jitter.......

In a nutshell, the PSRR of a simple CMOS gate is -6 dB at the midpoint. Both halves are going from the full on to full off state. So, each are on (or off) by the same amount.

Translation: the output is an open spigot to whatever noise is on the supply rail. And you can bet there is a lot of noise on the Xilinx supply. I don't know diddly about that chip, but in general, the less ground pins, the more crud you will have to deal with. With only one supply or ground pin, everything has to go through it. With its intrinsic inductance. Ergo, curd on the rail. And possibly ground bounce, as well.

For a 256 x Fs clock, those of us who design this stuff all seem to agree that the jitter has to be in the single pSec or so range. There is no way that you can get jitter that low out of any large chip. It is hard enough using single gate devices.

The other thing that you will need to consider is how to get the signals from point A to point B. Two ways: coax and ribbon.

I have used the ribbon cable method lots of times. But for very short lengths. A few inches. It will radiate. And then you have to drive it properly. Ribbon cable will be in the 110-128 ohm range. So, that means that you should drive it with that impedance.

Just stick that resistor at the output of the gate, right?

Wrong. You have to account for the gate's impedance. Somewhere in the 20-30 ohm range.

You also have to factor in the load capacitance, and how it will limit the HF content with a 120 ohm source. BTW, put the resistor as close to the drive gate as possible. You may find that you are losing too much BW. Maybe.

OK, so what if you use 75 ohm coax? Well, less EMI. Better BW. Even with RG-187 (or whatever number that tiny stuff is), you are going to have 4 coax cables to futz with. And you have to pay attention to the ground returns. They all have to go to the same point on both ends. Kinda messy. I know......

It really gets messy if you have to use 2 DAC chips. I'll skip that, since that is most likely not your scenario.

And since you want both 44.1 kHz and 48 kHz operation......if you think about what a nightmare it would be to have 2 clocks after the Xilinz, and then find some way to switch them........well, now you know why Sean has the Xilinx in the first place. Catch 22.

OK, your turn to digest and ponder.

Pat