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  1. #41
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    Here's a schematic I drew up for someone else doing exactly the same thing. Note I have not actually implemented exactly this schematic, in my DAC I'm using an FPGA to do the converting etc, but this SHOULD work, I've simulated this and it does the right thing.

    Note the circuit for shfting the data from left justified to I2S is a little complicated, this is to make sure that you don't have a race condition at the input to the DAC. The basic concept is the data gets clocked by the bclk which shifts it over by one so its I2S spec. What this does is clock data by the reclocked bclk, then clock it again by a reclocked inverted bclk, then the output is reclocked again. The net result is that the delayed data has exactly the same timing in relation to the other signals as the original data has, thus almost guranteeing you won't have a timing problem.

    The voltage conversion is done with HC logic run off 3.3V, since its 5V tolerent it works fine with this. In this cicuit I've specified the Tent 5V shunt regulator to run everything except the inverters driving the SB3. You certainly can use another regulator, but using the Tent makes this really easy, its hard to design your own regulator that will work as well as this and cost significantly less.

    Note I'm using a 174 to do the actual reclocking, this flies in the face all the conventional wisdom, there IS a reason for that. It depends on how you are building this. If you are using a PC board with SMD parts the best way is the "pico gate" single gate chips, these work wonderfully well for this. If you are using through hole parts and hand soldering things up I personally think the 174 is a better compromise. Because the DIP chips are so much larger they have much more capacitance and inductance on their package pins, using 4 or five of these will degrade the clock driving all of them worse than the jitter inside the one chip. Using 74s with both flops used is also not bad, thats kind of a wash with the 174. I definately would not use DIP 74s and only one flop per package, that sounds worse than a 174.

    I hope this helps.

    I definately think its worth the effort to get this up and running.

    John S.

  2. #42
    Fantastic! You are very generous John. Having a little difficulty reading the small font for component ID on the schematic. Would it be possible to post a file attachment or send pm? Thanks, Mike

  3. #43
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    Soon I will try again. This time I want to do it right so I also ordered a XO3 module from Tentlabs and use that instead of my self build version.. Advantage of that is that can also reclock the spdif output from the SB3 before it goes to the DAC. A more expensive solution but with a higher chance of succes.

    To avoid misunderstandings: I'm purely talking about building a proper external low jitter clock for SB3. No slaving from the DAC yet.

  4. #44
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    OK,
    here is a link to the full sized version.

    http://johnswenson1.home.comcast.net/stereo/SBI2S.gif

    I hope this is more readable.

    John S.

  5. #45
    Perfect. Thanks John!

  6. #46
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    A tale of clocks and DAC

    Hi folks,

    I take the opportunity of reporting my own modest experience with clocks and SB. Actually, it's a SB2 I played with, so components references and pinout in the following may differ for a SB3.

    I elected a D-Clock from NewClassD, the new home for Lars Clausen, formerly at LCaudio. Advertised intrinsic jitter is a mere 1.5 ps. Small enough, I guess. So I ordered a 11.2896 MHz clock, keeping the 12.288 MHz part of the circuit untouched.

    The output of this clock is floating, using a pulse transformer.
    At first, I ried to connect the cable directly to pin#42 of the Xilinx, after cutting the trace between this pin and the pin#2 of the HCU04. My concern was not to use the crystal pad, as this one is fed through two successives gates before it gets to the Xilinx FPGA. And these gates are not free of any power supply noise, which is a well known cause of jitter.

    A convenient ground was found by inserting a short piece of thin component lead (from a signal diode, I think) in a via close to the Xilinx. Just peel of the varnish on the bottom side of the PCB, then gently scub the ground plane in order to make a good solder. After that, you get some kind of a robust pin to hook the cable shield to.

    Adequate power supply was obtained from the pins of the conspicuous big 3300ÁF cap in the vicinity.

    Alas, it didn't work: as reported by another member in this thread, no progression on the timing bar.

    I drop a line to Lars Clausen, and he was kind enough to answer back promptly. I followed his advice to go first through a gate of the HCU04, assuming that this device would be more compliant to the symetric, low voltage, clock output (actually, it's a +/-1.6V instead of a 3.3V). He added that the transitions of his clock are very sharp, and shouldn't be affected jitterwise by the HCU04. However, I decided to keep the gate count as low as possible: no more than one!

    So I connected the clock cable to pin#1 of the HCU04, actually using one of the pads of the previously removed 12.2896 MHz crystal. Of course, I repaired the previously cut trace between the output of this gate (pin #2) and Xilinx pin#42.

    This setup works perfectly now.

    In order to get clean of unwanted signals, I removed also the caps C6 and C15 (the small companions of the crystal) and, as a final touch, I lift up the pins #3 and #4 of the HCU04, effectively removing of the circuit the Pierce oscillator gate.
    Doing this, I'm pretty sure there is no other component involved in the path of the clock output. Oh, yes, one end of the resistor R1 (the one paralelling the crystal) is still connected to it... but the other end is now floating around, so it shouldn't hurt.

    This is for my story: I hope it will be helpful for somebody.

    Well, now it works, and well, but does it worth the expense?
    If using the analog out of the SB, maybe yes, assuming you also do your homework on power supply and the like.
    But if you go for a first class external DAC, and in my humble opinion: no.

    Last month, I purchased a Lavry DA10, and, as I also own an untouched SB3, I set up some comparison, one SB using the Toslink, and the other the coax: the Lavry allows for a convenient switching between these inputs.

    I felt unable to tell a difference. I exchanged the connection, too, in order to eliminate possible difference in electrical vs. optical interface.

    I made some spectrum analysis, using the sound pattern from Julian Dunn, and I must say there is some improvement in the picture for the reclocked SB2 over the stock SB3. All well below the -130 dB theshold. Hardly audible.

    As a matter of fact, I'm wondering if the guys at Slimdevices didn't do some fine tuning in the SB3 over the SB2, with improved PCB layout, or different components, I don't know, but my feeling is that the SB3 is slightly better than the SB2, regarding jitter (I didn't pay much attention to analog output, however).

    So this is my (not so humble) advice: don't bother modding the SB3. Just buy a decent DAC. The Lavry DA10 is a dream, BTW.

    JLM
    Last edited by jlmatrat; 2007-04-02 at 08:14.

  7. #47
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    Very nice post! Thanks for going to the trouble. I haven't sent my stuff for the mods yet and I'll take your experiences into account.

    Mike

  8. #48
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    My SB3 is running now on an external clock (XO3 module from Tentlabs). Also the spdif output is relocked now before send to the DAC.

    Now I'll need some time to listen and to compare it to my cd transport. First impression is that the differences between the two have gotten smaller!
    Last edited by tingtong5; 2007-04-07 at 05:24.

  9. #49
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    The WAF must be through the roof on that mod! :-)

  10. #50
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    Quote Originally Posted by Mark Lanctot View Post
    The WAF must be through the roof on that mod! :-)
    FÍck the WAF! (literally)

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